The present invention relates generally to semiconductor memory devices. More particularly, the present invention relates to a voltage boost level clamping circuit for a flash memory.
In the design of integrated circuits, there is a trend to power the integrated circuits using decreasing power supply voltage levels. Previous circuit families operated at 5 volts and 3.3 volts. Current families operate at 1.8 volts and future families will operate at or below 1.0 volts nominal supply voltage, for example at 0.8 volts. These lower power supply voltages create design and operation challenges.
One design challenge relates to accessing a storage element or core cell of the memory device. The voltage swing available in low supply voltage systems such as a 1.0 volt supply system is typically insufficient for a read or a program of a flash memory cell. Accordingly, boost circuits have been developed to provide the necessary voltage variation. For accessing the core cell, a word line voltage is boosted to, for example, 3.2 volts. This allows the core cell transistor to fully turn on and the core cell to sink enough current for rapid sensing of the state of the cell by the sensing circuitry.
A high boosted voltage is generally required in a low supply voltage system such as a 1.0 volt supply system. In order to generate this high boosted voltage, a multi-stage booster circuit can be used with an effective boost ratio. However, the effective boost ratio characteristic is substantially linear and for a supply voltage higher than a certain value, the effective boost ratio yields a boosted voltage that is higher than desired.
The approximate range of supply voltage presented to a chip or a memory device can vary depending on the application. Of course, supply voltages can also vary over the lifetime of a device as well. In many flash memory applications, for example, batteries are often utilized to provide a power supply. The supply voltage presented to a memory device by a battery can decline with time and usage, yet consistent performance at all stages of use is desirable.
It would be desirable to provide a method or apparatus to prevent boosted voltages from becoming too large in size. It would also be desirable to utilize booster circuits responsive to a flexible range of voltages while still achieving desired performance.
By way of introduction only, an embodiment of a voltage boost circuit for a flash memory is presented. The voltage boost circuit includes a boosting circuit to boost a portion of a supply voltage of the flash memory to a word line voltage level adequate to access a core cell of the memory. The voltage boost circuit further includes a balancing circuit to provide a nonzero adjustment voltage to the boosting circuit to reduce the portion of the supply voltage that is available for boosting by the boosting circuit when the supply voltage exceeds a certain value.
An embodiment of a voltage clamping circuit for a memory for use in conjunction with a voltage boost circuit for boosting a supply voltage is presented. The voltage clamping circuit includes a feedback loop that further includes a first transistor that has a threshold voltage that serves as a clamping voltage. The feedback loop additionally includes pull up and pull down transistors coupled to the first transistor to stabilize the feedback loop to provide a stable voltage to the voltage boost circuit. The stable voltage reduces the portion of the supply voltage that is available for boosting by the boosting circuit.
An embodiment of a voltage boost circuit for a memory is also presented. The voltage boost circuit includes a boosting circuit and a clamping circuit. The boosting circuit is coupled to a boosted node to boost a word line voltage to access a core cell of the memory. The clamping circuit is coupled to the boosting circuit, and includes a threshold voltage clamping transistor to clamp the boosted node to a desired voltage.
Also presented is an embodiment of a memory, including a core cell array, an address decoder, a boosting circuit, and a balancing circuit. The address decoder is configured to activate one or more word lines of a plurality of word lines. Each word line of the plurality of word lines is associated with one row of the core cell array. The boosting circuit is configured to boost a portion of a supply voltage of the memory to produce a boosted voltage on a boosted node coupled to the address decoder. The address decoder responds to the boosted voltage by boosting the word line voltage of one of the one or more word lines upon activation to a boosted voltage suitable to access a core cell of the core cell array. The balancing circuit is coupled to the boosting circuit and provides a nonzero adjustment voltage to the boosting circuit to reduce the portion of the supply voltage that is available for boosting by the boosting circuit when the supply voltage exceeds a certain value.
An embodiment of a method, for use in a memory, of clamping a boosted voltage to an acceptable level is presented. An adjustment voltage is generated with a balancing circuit. A portion of a power supply voltage of the memory is boosted to a boost voltage with a voltage boost circuit. The boost voltage is clamped to an acceptable level by utilizing the adjustment voltage to reduce the portion of the power supply voltage that is available for boosting.
Another embodiment of a voltage boost circuit for a memory is presented. The voltage boost circuit includes a means for boosting a portion of a supply voltage of the memory to a boost voltage. The voltage boost circuit also includes a means for generating an adjustment voltage. The voltage boost circuit further includes a means for clamping the boost voltage utilizing the adjustment voltage.
The foregoing discussion of a series of the presently preferred embodiments has been provided only by way of introduction. Nothing in this section should be taken as a limitation on the following claims, which define the scope of the invention.